1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically to a semiconductor memory device provided with a spare memory cell for replacing a defective normal memory cell.
2. Description of the Background Art
A conventional DRAM (Dynamic Random Access Memory; hereinafter referred to as a semiconductor memory device) will be described with reference to FIG. 10. As can be seen from FIG. 10, a conventional semiconductor memory device 9000 includes a plurality of normal memory cells arranged in a matrix of rows and columns, a plurality of normal word lines 91#1 to 91#4 corresponding to the rows, a plurality of bit lines 93#1 to 93#4 corresponding to the columns, spare word lines 92#1 to 92#2 which can replace normal word lines, and a plurality of spare memory cells for replacing defective normal memory cells.
The normal word line and the spare word line are connected to a row decoder 80, and set to a selected state in accordance with a row address input to an external address input terminal (not shown). Row decoder 80 includes redundancy circuit for selecting, when an input row address corresponds to defective address, a spare word line corresponding to the defective address.
Bit lines 93#1 and 93#2 are connected to a sense amplifier 82#1, and bit lines 93#3 and 93#4 are connected to a sense amplifier 82#2. Sense amplifiers 82#1 and 82#2 are connected to a column decoder 84, and set to a selected state in accordance with a column address input to an external address input terminal (not shown).
Reference characters 94#1 to 94#8 of FIG. 10 represent storage nodes of capacitors included in normal memory cells, and reference characters 99#1 to 99#4 represent storage nodes of capacitors included in spare memory cells. Reference numeral 95 denotes a source/drain region. For example, a memory cell including storage node 94#1 is selected by normal word line 91#3. Thus, stored charges are transmitted through a bit line contact 98 to bit line 93#1.
In such a structure, when the normal memory cell including storage node 94#1 is defective and an activating signal for selecting normal word line 91#3 is generated, row decoder 80 operates not to activate the normal word line but to activate spare word line 92#1. Accordingly, charges of the spare memory cell are transmitted to bit line 93#2. Sense amplifier 82#1 amplifies charges of the spare memory cell including storage node 99#1, instead of the normal memory cell including storage node 94#1. More specifically, normal word line 91#3 is replaced by spare word line 92#1, whereby the normal memory cell connected to normal word line 91#3 is replaced by spare word line 92#1, whereby the normal memory cell connected to normal word line 91#3 is replaced by spare memory cell connected to spare word line 92#1.
In the conventional semiconductor memory device, the normal word lines and spare word lines are the same structure, and normal memory cells and spare memory cells are manufactured to have the same size.
Therefore, normal memory cells as well as spare memory cells may possibly be defective.
When the spare memory cell does not normally function because of the defect, however, a defective normal memory cell, if any, cannot be repaired. Therefore, it is desired that the possibility of defects in the spare memory cell is lower than in the normal memory cell.